(1) Field of the Invention
This invention relates to an address translator and an address translation method and, more particularly, to an address translator and address translation method for translating a virtual address to a real address.
(2) Description of the Related Art
Because of recent increase in resources, various systems increasingly require large real address spaces, and more flexible and inexpensive address translators are demanded. For address translators, there is a virtual memory scheme for translating virtual addresses specified by a program to real addresses presented to a real memory, and this scheme greatly eases limitations on memory space.
Some of conventional address translators adopting the virtual memory scheme are provided with address translation buffers which are switched according to a supervisor mode or a user mode. The address translation buffers for the supervisor mode are not required to hold process numbers, resulting in saving memory resources (for example, refer to Japanese Unexamined Patent Publication No. 6-52058 (Paragraph [0016]-[0018], FIG. 1).
Now more systems offering real-time processing run a plurality of Operating Systems (OS) with a hybrid method.